Sounds like AMD is working on something very interesting. According to the sources, they are actively working on a 15-matrix design for EPYC AMD Milan. Considering that one of them must be an IO cube, this means that there will be at least one Milan variant with 14 cubes compared to Rome’s 8.
Currently, a rumor is circulating that at AMD Milan – the next-generation Epyc processors – HBM2 should be installed as a cache on the package.
According to Wccftech, speaking to an engineer, some of these 14 matrices would be HBM memory.
The DDR4 has a bandwidth of only 8 channels to optimally process a maximum of 10 CPU arrays (80 CPU cores). This means that they are looking for an 8-array design (64 CPU cores) or a 10-array design on the CPU side. Apart from the IO matrix, 6 or 4 of these are ignored and are likely to end up as HBM memory, depending on speculation.
AMD EPYC Milan would be a new revolution
With HBM, there can be significant acceleration, but this means that this particular variant will use an interposer. In short, this means that it is either an 8+6+1 configuration (CPU + HBM + IO) or a 10+4+1 configuration (CPU + HBM + IO) unless AMD decides to move this variant to DDR5.
Designing interposer-based with HBM on board could provide much faster access and transfer times than traditional DDR-based memories where there is a DDR channel bottleneck. This will lead to some significant accelerations for applications that are heavily memory dependent.
It is worth mentioning that earlier leaks indicate that AMD Milan has an 8+1 design. Depending on how this is interpreted, it could mean that Milan has two variants. We will keep you informed.