TSMC is detailing the performance improvements to be offered by its N3P and N2. The world’s leading advanced chip wafer maker is giving us a preview of the improvements to be offered by its upcoming process nodes.
TSMC: N3P and N2 Node Enhancements to be Delivered in Detail
TSMC is the manufacturer selected to manufacture the next processors for AMD, Apple, Nvidia and many other technology companies. The nodes are extremely important to be able to manufacture increasingly advanced and complex chips in terms of number of transistors and power consumption.
The manufacturer has been investing a great deal of money in R&D over the past few years. All of that investment translates into this revealed roadmap, which shows performance improvements with the upcoming 3NP and N2 process nodes, something that was discussed by TSMC’s Kevin Zhang.
The manufacturer expects its N3P node to increase performance by 18% with the same power as an N5 chip, in addition to reducing power consumption by 32% with the same performance levels. They also comment that the transistor density (logic) will be increased by 60% and the total density by 30% with respect to N5 (5 nm).
With respect to the N2 node, it will go into series production in 2025. They expect a power reduction of 25 to 30% with respect to N3E and a performance increase of 10 to 15% with the same power. Density is expected to increase by 15%.
These new nodes will apply performance and efficiency improvements on their own, not counting the architectural changes that will be applied by companies such as AMD, Nvidia or Apple, which are some of TSMC’s main customers.