ARM updated the big.LITTLE architecture in March with a DynamIQ call. While the former allows the creation of homogeneous clusters of cores of the same type, the second allows the creation of heterogeneous groups of cores of different types. Now TSMC, Xilinx, ARM, and Cadence have announced that they will test a chip made in a 7 nm FinFET node using this technology in the first quarter of 2018.
The focus is on a data center chip, which will also test a new coherent cache of accelerator cache (CCIX). That will communicate this multi-core chip with FPGA accelerators. So, it is a chip that is reprogrammable, simpler and more efficient than a current CPU. Also, a field in which Xilinx has a lot of experience – external to maintain the coherence of the information accessed by the whole – always have access to the most current information processed throughout the system in the main memory.
TSMC 7nm technology
The underlying idea is that they can communicate with this interconnect chips of different types. So, causing each chip to process the information for which it is more prepared. It is a critical point for data centers, which usually handle massive amounts of information of all kinds, and usually, end up executing information in a processor when they could do it in a FPGA if they could ensure the coherence of the information.
7 nm chip road map from GlobalFoundries
They promise greater bandwidth and lower access latencies with their new CCIX. The chip uses cores based on the ARMv8.2 architecture, the CMN-600 interconnect, with DDR4 memory and access to PCIe 3.0 / 4.0 tracks via controllers provided by Cadence. If all goes well, after the tests of the T1 of 2018, the chip will go on sale in the next half of the year.
Source: TSMC . Via: AnandTech .
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