SK Hynix presented its storage product roadmap for the next 10 years and was pleased to announce its plans for what the company calls 4D NAND. Before going ahead that they are adding to the dimension of time in the equation or that they have revolutionized physics with a 4th spatial dimension, we already make it clear that this is not the case.
What is CTF Technology?
To explain the new technology, you first need to remember what is 3D NAND? In a basic explanation, the technology consists of vertically stacking the storage cells to reduce the space and cost of the product in general. For this purpose, companies such as Samsung and Western Digital use an architecture called Charge Trap Flash (CTF), in which silicon nitrate is used to store the electronics. In the end, the big advantage is that the final production price of the memory is reduced.
4D NAND’s major innovation is a new CTF project that positions the peripheral circuit embedded in the memory cells instead of their side – as Samsung and WD do. Like all the technologies mentioned above, the space requirements of the product are reduced and the costs for its production are therefore lower.
How CMOS under Array works?
According to Tom’s hardware side, a very important detail is that the technology is not necessarily a novelty. Intel and Micron have never done anything like this with their 3D flash memory because they are referred to as CMOS under Array (CuA). Samsung also showed that it plans to use a CuA project in a similar way to in the future.
Despite Disso, Hynix’s roadmap is impressive. The company plans to introduce its first generation of 4D NAND memories by the end of 2018. They are also developing the QLC 4D NAND memory, which is expected to be released in the second half of 2019.
SK Hynix expects to achieve 4D NAND 500 GB memory in the future, but the company does not specify the date by which it will achieve this.