As planned, SK Hynix introduced the so-called “4D-NAND” in this quarter, which will go into series production this year. SK Hynix has just released the first 4D NAND Flash Chip based on CTF 96 layers at 512Gb. These chips are based on their TLC matrices using 4D Charge Trap Flash (CTF) design in combination with Peri Under Cell (PUC) technology. According to SK Hynix, the combination of both is the first in the industry. Although there have been earlier prototypes of integrating 3D Floating Gate with PUC.
The 4D NAND chip reduces the size of the chip by more than 30%. In addition, the productivity of bits per wafer increases by 49% compared to 72 Layer 512 Gb NAND 3D. The product has 30% more write and 25% more read performance. In addition, the bandwidth is doubled to 64KB, the largest in the industry.
With the introduction of a multi-port insulator architecture, the IO data rate reaches 1,200 Mbps at 1.2 V operating power.
When can we see 4D NAND products?
The 3D NAND chips were introduced by Intel and Micron and called CMOS Under Array (CUA) technology, in which the peripheral circuits are not to the side but below the levels of the memory cells. SK Hynix now uses a similar principle and talks about the Periphery Under the Cell (PUC). This saves space compared to the conventional design, where the I/O zone is located at the edge of the chip. Smaller chips mean lower costs.
SK Hynix will begin the first stage of mass production of 96-layer 4D NAND this year. A single 512Gb NAND flash chip can be converted to 64GB memory.