AMD could introduce a level 4 cache, or L4 cache, with its fourth-generation Ryzen CPUs and the EPYC Genoa ‘Zen 4’, which could help with the ever-increasing number of cores available through Zen chips.
AMD Ryzen and EPYC ‘Zen 4’ could have L4 cache
There have been rumors that the amount of cache memory in the Zen 4 architecture could double as a result of the increased data density provided by the 5 nm EUV node. The patent shared by Underfox illustrates the addition of a new L4 cache in virtual environments:
To date, AMD’s Ryzen and EPYC processors have an L1 and L2 cache that is unique to each core. The L3 cache is then shared by the cores in a CCX. It is reported that fourth-gen Zen will unify the L3 cache to serve the entire CCD (2x CCX). This new patent includes the possibility of an L4 cache that handles the L3 cache errors that occur on CCDs and serves essentially the entire CPU.
AMD recently introduced an L3 cache with its Navi GPUs, while NVIDIA’s Turing series still has two levels of cache. However, here the L4 cache is primarily aimed at virtualized environments where multiple users share the same processor or processor set. It is not clear how a common L4 cache for all CCDs can improve performance, especially considering that they are used by different users. So we will have to wait for more information on this.
The core area of the next generation Zen sample is said to be about 80 square millimeters, which means that the Zen 4 still uses a multi-chip package-chiplet design, and the area is about 10% larger than the 74 square millimeters of the Zen 2. And according to TSMC, the 5nm will increase the transistor density by 80% compared to 7nm, so it seems that the number of transistors in the Zen 4 should be doubled. The EPYC “Genoa” of Zen 4 will have the chance to reach 96 or even 128 cores, which will cause Intel to cry with tears.