AMD has confirmed new details about the 3D V-Cache technology for its Ryzen 70003XD series, as this is the second generation of chips with this technology after the 50003XD and the technology is not exactly the same in both cases, as we have learned…
It’s only been a week since the launch of the AMD Ryzen 7000X3D, but AMD has been pretty open about all the new features and details needed for this new version. That’s a rarity for such companies, which tend to hide details. But AMD isn’t stupid, and I’m sure they’ve held back a lot of things….
However, we do know some interesting details about the new second-generation 3D V-Cache and how it differs from the one used for the Ryzen 5000X3D units. In addition, over the weekend AMD made another grand gesture to publicize the technology, releasing images of the new I/O array or cIOD used in the current 8-core CPUs (Raphael).
First of all, it is important to know that the 3D V-cache of the Ryzen 7000X3D series has been expanded to 96 MB at the L3 level for one of the chips in the package. This cache was developed in a 7nm manufacturing process, while it is located on a 5nm manufacturing chip (CCD).
Despite the 7nm size, the new second-generation 3D V-Cache chip is smaller than the first-generation chip, while the number of transistors has remained the same. This means that the transistor density has increased from 114.6 million to 130.6 million transistors/mm².
AMD Ryzen 9 7950X3D second generation 3D V-Cache technology.
On the other hand, AMD has also confirmed that the new 3D V cache has a higher bandwidth than its predecessor, reaching no less than 2.5 TB/s. This means a speed increase of 25%, or 0.5 TB/s, since the first-generation cache used in the Ryzen 5000X3D only reached 2 TB/s.
To make this possible, AMD had to modify the chip-to-chip connections, i.e. the TSVs (Through Silicon Vias), and reduce the TSV area by 50% to connect the cache chip on the compute chip.
AMD is using the same Zen4 CCDs for the 3D V-Cache chips as for the Ryzen and EPYC series, but the I/O die has been changed for consumer processors and for processors intended for high-performance or data center environments. However, an image of the consumer I/O chip was shown on the slides, as seen in the image above.
The dieshot was on display at AMD’s presentation at ISSCC. And it didn’t take long for many semiconductor fans and experts to analyze it in detail, such as the user known as Louza and other media. Another important detail of the cIOD is that the integrated GPU is now located inside it, and not next to the CPU cores as in APUs.
This iGPU is limited to 128 GPU cores, as can be seen in the image. Furthermore, it is confirmed that the input/output array only has two GMI (Global Memory Interconnect) ports, so triple CCD configurations are not possible in this chiplet design.
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