TSMC announced that it will be the first in the world to develop the CCIX (Cache Coherent Interconnect for Accelerators) interface for the next year. This CCIX is a standard memory coherent interface, which will become a more critical factor in the server market, not by chance a gigantic consortium with a number of major industry players.
CCIX Technology?
CCIX itself is a huge promise. As it does not have to commit itself to a specific accelerator on servers built on that. For example, the server can be purchased with a GPGPU accelerator. But if it turns out that FPGA or DSP is better for that task, it is possible to replace the accelerator without replacing the entire server. Which is obviously a cost-benefit factor.
The TSMI plans to launch the demonstration for 2018, and the tile is expected to be available in the second half of the year. The design for the test is planned with the assistance of ARM, Cadence, and Xilinx at TSMC, 7 nm node. The test sheet is ARM DynamIQusing the ARMv8.2-A instruction-based core and the ARM CMN-600 caching coherent bus. Critical I / O interfaces.
7 nm chip roadmap from GlobalFoundries
That includes CCIX, and the memory system is designed by Cadence. And the latter is also responsible for the control and deployment tools. The role of Xilinx is that they provide the Virtex UltraScale + FPGAs. That is able to connect via the new technology to the designed chip. The FPGAs of the Virtex UltraScale + HBM family. That is based on the 16 nm node of the TSMC and the CoWoS technology, will not only test products. But also truly buyable solutions that include CCIX support. So if the first, actually available, CCIX support platform, it will be used immediately with Xilinx’s novelty.