Western Digital works with the open RISC-V instruction sets (ISA), which allow anyone to create a processor design without paying any license fees or royalties. Finally, the company announced the SweRV RISC-V processor with an open source license.
Western Digital announces SweRV RISC-V processor
In 2017, the company committed to switching its warehouse processing products to RISC-V to deliver one billion cores over the next two years. Nvidia has also begun to move from patented cores to RISC-V to control the input and output of its graphics products, Rambus uses RISC-V for safety components and has even found its way into SSD memory controllers.
The SweRV core itself is a two-sided superscalar implementation of the 32-bit variant of ISA RISC-V, which has a nine-tier pipeline capable of loading multiple statements and executing them one after the other simultaneously. The core currently implemented in a 28nm CMOS processing node that runs at up to 1.8 GHz and achieves an estimated throughput of 4.9 CoreMarks per megahertz.
Western Digital has confirmed that it plans not only to use SweRV in its own products but also to distribute it under an open source license. This has already happened with two supporting technologies: the SweRV Instruction Set Simulator (ISS), which allows interested parties to test the kernel; and OmniXtend, which implements a coherent cache over an Ethernet fabric that focuses on everything from the CPU to the GPU and auto-learning coprocessors.
The SweRV will be launched in the first quarter of 2019, Western Digital confirms, what do you think of the announcement of this SweRV RISC-V processor with an open source license?