After TSMC’s presentation in Semicon West this year, the good people at Wikichip consolidated the company’s processing nodes and packaging plans. Although the N7+ is TSMC’s first EUV-based node, the chips produced with this technology are not the most advanced silicon used by EUV.
The first “complete” TSMC node after the N7 is the N5 Node with three intermediate nodes that take advantage of the IP and design of the N7.
First 5 nm TSMC chips arriving in 2021
Behind the N7 node is TSMC’s N7P process, which is an optimization of the first based on DUV. The N7P uses the design rules of the N7, is IP compatible with the N7 and uses FEOL (Front-end of-the-line) and MOL (Middle-of-line) improvements to achieve a 7% performance increase of 10% energy efficiency increase.
Risk production for TSMC’s 5nm node, the so-called N5 Node, began on April 4, and a single report from Taiwan suggests that the process will end in mass production after next year (2021). TSMC expects production to increase in 2020 and the plant has invested heavily in process development as N5 Node is the first true successor to N7 with EUV.
N5 Node chips are twice as dense (171.3 MTR/mm²) as N7 chips and allow users to achieve 15% more performance or reduce power consumption by 30% compared to N7. However, FEOL and MOL optimization take place in the N5P. It will improve N5P performance by 7% or energy consumption by 15%.
As a result, PC processors and SoCs, mobile devices, 5G, and other devices are approaching a new era that will improve their performance and enable greater energy savings.