TSMC and MIT could use bismuth to accelerate Moore’s Law

It seems that National Taiwan University, MIT, and TSMC have managed to develop a solution that could simplify the development of 1nm lithography by using bismuth (Bi).

Bismuth is the solution for the 1nm node, according to TSMC, MIT, and National Taiwan University

Currently, TSMC’s 7nm and 5nm nodes are in operation and chips can be created under these lithographs. The problem is that as we progress down the size of the node, we run into the problem of the physical limit of silicon. Moore’s Law is slowed down by the difficulties already encountered with today’s nodes, which are progressively becoming smaller.

At present, the most advanced nodes available for mass production would be the TSMC 5nm and 3nm, they are the first ones ready for mass production. The problem is that when we talk about the 1.5nm and 1nm nodes, there are physical problems because they are so close to the physical limit of silicon.

As a solution to this problem, we decided to use semi-metallic bismuth (Bi) as a two-dimensional contact electrode. This structure reduces the resistance of the material and significantly increases the current. One of the most interesting points is that the performance would be comparable to silicon. In addition, this material can overcome the challenge of making 1nm transistors.

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The process to achieve the possible use of Bi was not easy. The first step was taken thanks to MIT, which developed the first semi-metallic bismuth electrodes. Then TSMC optimized this process in terms of the arrangement of this material. Finally, National Taiwan University managed to reduce the size of the channels to manometric using helium ion beam lithography.

Status of the various TMSC nodes

TSMC currently offers the 7nm node for both large processors (such as Ryzen) and SoCs. The 5nm node is currently reserved for SoCs only, although it could be available for large chips by the end of the year.

According to the Taiwanese manufacturer, they could start producing chips under the 4nm node in the risk phase by the end of this year. This means that a large portion of the chips would be defective and the manufacturing process would need to be polished up to achieve profitable production. It is estimated that by May 2022, 4nm lithography will be ready for SoC manufacturing.

The company estimates that it could start risk manufacturing under the 3nm node in the second half of 2022. They also note that the 2nm node is currently under development.