Micron has begun sampling LPDDR5-based uMCP products.
In a press release today, Micron announced that it has begun sampling the industry’s first low-power DDR5 DRAM (LPDDR5 DRAM) Universal Flash Memory (UFS) multi-chip package (uMCP).
The new uMCP5 package can combine low-power DRAM with NAND and onboard controllers and requires 40% less space than a two-chip solution with separate DRAM and NAND. The uMCP5 package with LPDDR5 DRAM is designed with high density and low power consumption for slim and compact midrange smartphone designs.
The Micron uMCP5 uses advanced 1y nano DRAM process technology and the world’s smallest 512 Gigabit 96 layer 3D NAND chip (512Gb 96L 3D NAND). The 297 BGA package supports dual-channel LPDDR5 operation at speeds of up to 6,400 Mbps and offers a 50% performance increase over previous generation interfaces. The maximum available memory density for the uMCP form factor is 12 GB RAM and 256 GB UFS memory.
According to Micron, uMCP is the ideal solution for LPDDR5 DRAM, and the next generation LPDDR5 memory can process data at speeds of up to 6.4Gbps, meeting the high memory performance and low power consumption requirements of 5G networks worldwide this year.