While we are waiting for the announcement of the Zen 3 based Ryzen 4000 processors (tentative name) on this October 8th, the CyberPunkCat hardware filter has just sent us a preview of the upcoming product.
AMD Ryzen 4000 Zen 3, Confidential details about Vermeer leaked
The information, dated June 10th, appears to have been taken from internal AMD documentation. Although the information appears legitimate, we recommend that it should be treated with some caution.
The document is a Processor Programming Reference (PPR) guide for the AMD family 19h Model 21h B0. Since Zen(+) and Zen 2 belong to the 17h family, family 19h should be for Zen 3.
The Ryzen 4000 series processors (codenamed Vermeer) will retain the multi-chip design (MCM). Zen 3 will house two Complex Core Chips (CCD) with an IOD die in one chip package. Externally, the configuration looks identical to Zen 2, but it is not.
In Zen 2, each CCD houses two core complexes (CCX), with each complex consisting of four cores sharing 16 MB of L3 cache. According to the AMD paper, the composition of Zen 3 is completely different; within each CCD there is only one CCX. The CCX has eight cores that can operate in single-thread (1T) or two-thread SMT (Multi-Threaded Simultaneous) mode (2T), for a total of 16 threads per complex. Since there is now only one CCX, all eight cores of the CPU can directly access the 32 MB of the shared L3 cache.
In Zen 3 the L3 cache is still 32 MB per CCD. In Zen 2, the four cores within each CCX only have direct access to 16 MB L3 cache, while in Zen 3 the eight cores within the CCX share the same 32 MB L3 cache. The new design should reduce latency and improve instruction per cycle (IPC).
It also shows that Zen 3 has two Unified Memory Controllers (UMC), one per channel. Each channel supports up to two DIMMs. Also mentioned is the scalable data structure with a capacity of up to 512 GB for each DRAM channel. In terms of memory speeds, Zen processors with native support for DDR4-3200 are delivered on the same line as the Zen 2.
Although it is not mentioned in the documentation, we should see a series that improves the clock frequency and certainly reaches 5 GHz or stays at the gates of those frequencies that already reach the Intel core chips.