Official information has been released about AMD’s next-generation CPU family, the Ryzen 5000 Vermeer series, based on the Zen 3 architecture. The information is part of confidential AMD documents provided to WCCFTECH by CyberCatPunk.
Although the new series will be officially introduced on October 8th, some specifications have now been leaked to give us an insight into the performance of these Zen 3-based CPUs. This architecture, which will probably be based on TSMC’s 7nm+ EUV process node, is expected to deliver better performance per watt and efficiency than the previous Zen 2 line, which was already a revolutionary architecture from AMD.
According to these filtered white papers, Vermeer CPUs will be designed for use in high-performance desktop platforms and will also feature up to two CCDs (Core/Cache Complex Dies) and a single IOD (I/O Die). The document is dated June 10.
Zen 3 will feature a CCX with more cores
Unlike the previous AMD generation, where a single CCD housed two CCXs (Core Complex), a single CCX in Zen 3 has up to 8 cores running in a single-threaded (1T) mode or in a two-threaded (2T) SMT (Multi-Threaded Simultaneous) mode for up to 16 threads per CCX.
The chip will have a maximum of two CCDs (Core Complex Dies), so that the number of cores and threads will reach a maximum of 16 and 32 respectively, as with the existing Ryzen 9 3950X desktop CPU.
According to the documents, there is only one CCX in each CCD. Therefore, all eight CPU cores can now directly access the 32 MB of the shared L3 cache. The amount of L3 cache remains the same at 32 MB per CCD in Zen 3. This new design, revised in Zen 3, will help reduce latency and also improve the overall instruction per cycle (IPC).
High-performance expectations
AMD will introduce an improved SDF (Scalable Data Fabric) with next-gen Zen cores supporting up to 512 GB per DRAM channel or up to 1 TB of ECC DRAM. For the memory interface, these Ryzen 5000 Vermeer desktop CPUs will continue to support DDR4-3200 speeds. However, there will be 2 unified memory controllers in the CPU, each supporting one DRAM channel for a total of 2 DIMMs per channel.
It is expected that the Zen 3 architecture will provide at least 15-17% IPC improvement over the Zen 2 CPU line of the previous generation. Zen 2 CPUs already had double the L3 cache on the Zen / Zen + series chips, so Zen 3 will take things to a whole new level.
The next-generation Zen architecture aims to improve some of the shortcomings of AMD’s architectural designs. It is therefore expected that some of these CPUs will reach 5GHz to give Intel a tough competition on the single-core frequency, along with a 50% increase in Zen 3 operations and a major cache redesign.
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