AMD Zen 2 rocking once again with a remarkable achievement. Cache is a very important part of modern processors, and a major change in this part of the chip usually means that significant improvements in the processor. SANDRA points to major changes in the L3 cache of Zen 2.
An entry in SiSoft’s SANDRA database shows data about an AMD EPYC AMD processor and reveals the cache hierarchy of this model. Each 64-core Rome EPYC processor consists of eight-core Zen 2 chiplets manufactured at 7 nm converging into an E/S controller at 14 nm. This controller takes over the memory and PCIe connectivity of the processor. The result mentions the cache hierarchy with 512 KB dedicated L2 cache per kernel and “16 x 16 MB L3 cache”. For the Ryzen 7 2700X, SANDRA reads the L3 cache as “2 x 8 MB L3”, which corresponds to 8 MB L3 per CCX.
Since SANDRA recognizes “16 x 16 MB L3” for the 64-core Rom, it is very likely that each of the 8-core chips will have two parts of the 16 MB L3 cache and that their 8 cores will be split into two quad-core CCXs with 16 MB L3 cache each. This is especially important because the I/O die controls the memory with its 8-channel monolithic DDR4 memory controller.
AMD has made some profound architectural changes with Zen 2, we will have to wait until they go on sale to see what all these improvements really mean, but so far it looks pretty good.