AMD develops techniques for stacking DRAM and SRAM on processors using silicon channels for the connections between the matrices. Three-dimensional stacking technology must compensate for the fact that Moore’s law is over.
According to Tom’s Hardware, General Manager Forrest Norrod announced that AMD was working on 3D stacking of processor layers during the Rice Oil and Gas HPC conference. Manufacturers are already stacking chip plagues, but this applies to package-on-package technology, where the upper memory layers are connected with standard PGA connections. This enables efficient use of space but does not lead to high-speed gains.
According to Norrod, the reduction of chip structures no longer leads to frequency improvements. “With the next node, if we don’t do special things, there will be less frequency available,” he even says. The switch to smaller production processes has traditionally been accompanied by lower consumption and higher clock rates. This outcome of Moore’s law remains under pressure.
AMD therefore wants to connect stacked matrices with the help of push-through silicon vias. These are microchannels for fast data connections between the layers. Intel is working on similar techniques, which it presented last year under the name Foveros. Intel uses these techniques to combine chip components from different production processes, such as a 14nm i/o layer with a 10nm core layer. AMD is also working to make its processors modular. The company builds chipplets by connecting components with its CCIX-Gen-Z interconnects.