TSMC Unveils Wafer-on-Wafer Chip Stacking Technology

TSMC Unveils Wafer-on-Wafer Chip Stacking Technology

TSMC has taken advantage of the company’s Technology Symposium to announce its new Wafer-on-Wafer (WoW) technology, a 3D stacking technique for silicon wafers, which allows chips to be connected to two silicon wafers using through-silicon via (TSV) connections, similar to 3D NAND technology.

TSMC Unveils Wafer-on-Wafer Chip Stacking Technology

TSMC Announces Revolutionary Wafer-on-Wafer Technique

This TSMC WoW technology can connect two arrays directly and with a minimum of data transfer due to the small distance between the chips, this allows for better performance and a much more compact final package. The WoW technique piles silicon while it is still inside your original wafer, offering advantages and disadvantages. This is an important difference from what we see today with multi-die silicon technologies, which have multiple dies sitting side by side on an interposer, or using Intel’s EMIB technology.

The advantage is that this technology can connect two die wafers at the same time, offering much less parallelization within the manufacturing process and the possibility of lower final costs. The problem arises when faulty silicon is joined with active silicon in the second layer, which reduces the overall performance. A problem that prevents this technology from being viable for producing silicon that offers wafer-based yields of less than 90%.

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Another potential problem occurs when two pieces of heat-producing silicon are stacked together, creating a situation in which heat density could become a limiting factor. This thermal limitation makes WoW technology more suitable for silicon with low energy consumption, and therefore less heating.

Direct WoW connectivity allows silicon to communicate exceptionally quickly and with minimal latency, the only question is whether it will ever be viable in high-performance products.

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