AMD approaches the next Chiplet revolution with its new chip network scheme

Active silicon interleaves could make computers smaller and better, but networks need mesh.

Chiplet, AMD approaches the next Chiplet revolution with its new chip network scheme,

There may come a time when computers and other systems are not made of individually packaged chips connected to a motherboard with a printed circuit board, but of integrated circuits interconnected in a larger portion of silicon. Researchers have been developing this concept called chiplets with the idea that it will allow data to move faster and more freely to make computer systems smaller, cheaper and more integrated. The idea is that individual CPUs, memory and other key systems can be mounted on a relatively large portion of silicon, called an active interposer, which is full of interconnects and routing circuits.

“In a sense, if this is successful, it’s something similar to the story of integration (Moore’s Law and everything else) we’ve been talking about for decades,” says Gabriel Loh, Fellow Design Engineer at AMD. “It allows the industry to take a variety of system components and integrate them more compactly and efficiently together.

There is (at least) one problem: although the chip routing system itself of each chiplet can work perfectly when they are all connected to the interposer’s network, a situation can arise where a network tries to route data in such a way that traffic gets stuck and eventually takes over the computer. “A stalemate can basically occur where you have a cycle of different messages, all trying to compete for the same kind of resources, which makes everyone wait for each other,” explains Loh.

Chiplet, AMD approaches the next Chiplet revolution with its new chip network scheme,

“Each of these individual[chiplets] could be designed so that they never have dead spots,” says Loh. “But once I got them together there are new roads and new routes that no individual had planned ahead of time. Trying to avoid these new blockages by designing all chiplets together with a particular network of interleavers would defeat the advantages of the technique: chiplets could therefore not be easily designed and optimised by separate teams, and could not be easily mixed and matched to form new systems quickly. At the International Computer Architecture Symposium earlier this month, AMD engineers presented a possible solution to this impending problem.

A future system could contain a CPU chip and several GPUs, all connected to the same piece of network-enabled silicon.

The AMD team found that active interlocks in active interposers basically disappear if a few simple rules are followed when designing networks on the chip. These rules govern where data is allowed in and out of the chip and also restrict the directions it can go when it first enters the chip. Surprisingly, if you follow those rules you can pretend that everything else in the Interposer – all the other logical chiplets, the memory, the Interposer’s own network, everything – is just a node in the network. Knowing this, different teams of engineers can design chips without having to worry about how networks work on other chiplets or even how the network works on the active interposer.

It may be a while before this is necessary. So-called passive interpolations (silicon-containing interconnections but not network circuits) are already in use; AMD has been using one for its Radeon R9 series, for example. But adding a smart grid to the interposer could make a big difference in the way systems are designed and what they can do.