The Zen architecture is already a reality, and by mid-2019, this third generation of AMD Ryzen processors with a 7mm architecture should be officially released. These processors will be compatible with the AM4 socket and current motherboards, a great advantage that will also bring interesting information about these updates in the form of support code for Zen 2.
TechpowerUp shows a piece of interesting information about these AGESA 0.0.7.x updates from the hand of “1usmus”. We have found a number of new controls and options that are available exclusively for Matisse and also give hints on the new generation of Ryzen Threadripper processors. In addition, the name ” Valhalla ” appears in the “Common Options” section, which is very prevalent in the latest news about these Ryzen 3000 processors. In fact, it could be the codename of these Ryzen AM4 processors and the new chipset that brings the Southern Bridge to life as a replacement for the already familiar X470 called the AMD 500.
Undoubtedly, the chipplet architecture will allow AMD to implement the relevant updates for the new Zen 2 while retaining other 14 nm components. Of course, the 7nm processing core will presumably be built by TSMC, but other components such as the memory controller will continue to be built in the 14nm process by GlobalFoundries because it is more profitable and advantageous. In addition, AMD is expected to increase the core density on these chips by reducing the transistor size, thus increasing the number to about 12 or 16 cores.
Overclocking of RAM memory
Another innovation concerns the overclocking of RAM memory, and this was one of Infinity Fabric’s upcoming issues when the RAM modules were heavily overclocked. This I/O connection was synchronized with the frequency of the memory, so if the memory became too high, the interface could not handle such frequencies. Now the BIOS offers a number of UCLK options with three modes: “Auto”, “UCLK == MEMCLK” and “UCLK == MAMCLK/2”, the latter being the novelty. The “/2” makes it possible to scale the frequency of the I/O bridge in relation to the memory so that no synchronization between them is required and the frequency can be better synchronized. An example would be to set the RAM memory to a frequency of 1800 MHz and scale the memory I/O bridge to 1800/2=900 MHz.